Analog Integrated Circuit Design – David Johns, Kenneth W. Martin – 2nd Edition

CHAPTER INTEGRATED-CIRCUIT DEVICES AND MODELLING
1.1 Semiconductors and pn Junctions
1.1.1 Diodes
1.1.2 Reverse-Biased Diodes
1.1.3 Graded Junctions
1.1.4 Large-Signal Junction Capacitance
1.1.5 Forward-Biased Junctions
1.1.6 Junction Capacitance of Forward-Biased Diode
1.1.7 Small-Signal Model of a Forward-Biased Diode
1.1.8 Schottky Diodes
1.2 MOS Transistors
1.2.1 Symbols for MOS Transistors
1.2.2 Basic Operation
1.2.3 Large-Signal Modelling
1.2.4 Body Effect
1.2.5 p-Channel Transistors
1.2.6 Low-Frequency Small-Signal Modelling in the Active Region
1.2.7 High-Frequency Small-Signal Modelling in the Active Region
1.2.8 Small-Signal Modelling in the Triode and Cutoff Regions
1.2.9 Analog Figures of Merit and Trade-offs
1.3 Device Model Summary
1.3.1 Constants
1.3.2 Diode Equations
1.3.3 MOS Transistor Equations
1.4 Advanced MOS Modelling
1.4.1 Subthreshold Operation
1.4.2 Mobility Degradation
1.4.3 Summary of Subthreshold and Mobility Degradation Equations
1.4.4 Parasitic Resistances
1.4.5 Short-Channel Effects
1.4.6 Leakage Currents
1.5 SPICE Modelling Parameters
1.5.1 Diode Model
1.5.2 MOS Transistors
1.5.3 Advanced SPICE Models of MOS Transistors
1.6 Passive Devices
1.6.1 Resistors
1.6.2 Capacitors
1.7 Appendix
1.7.1 Diode Exponential Relationship
1.7.2 Diode-Diffusion Capacitance
1.7.3 MOS Threshold Voltage and the Body Effect
1.7.4 MOS Triode Relationship
1.8 Key Points
1.9 References
1.10 Problems

CHAPTER PROCESSING AND LAYOUT
2.1 CMOS Processing
2.1.1 The Silicon Wafer
2.1.2 Photolithography and Well Definition
2.1.3 Diffusion and Ion Implantation
2.1.4 Chemical Vapor Deposition and Defining the Active Regions
2.1.5 Transistor Isolation
2.1.6 Gate-Oxide and Threshold-Voltage Adjustments
2.1.7 Polysilicon Gate Formation
2.1.8 Implanting the Junctions, Depositing SiO2, and Opening Contact Holes
2.1.9 Annealing, Depositing and Patterning Metal, and Overglass Deposition
2.1.10 Additional Processing Steps
2.2 CMOS Layout and Design Rules
2.2.1 Spacing Rules
2.2.2 Planarity and Fill Requirements
2.2.3 Antenna Rules
2.2.4 Latch-Up
2.3 Variability and Mismatch
2.3.1 Systematic Variations Including Proximity Effects
2.3.2 Process Variations
2.3.3 Random Variations and Mismatch
2.4 Analog Layout Considerations
2.4.1 Transistor Layouts
2.4.2 Capacitor Matching
2.4.3 Resistor Layout
2.4.4 Noise Considerations
2.5 Key Points
2.6 References
2.7 Problems

CHAPTER BASIC CURRENT MIRRORS AND SINGLE-STAGE AMPLIFIERS
3.1 Simple CMOS Current Mirror
3.2 Common-Source Amplifier
3.3 Source-Follower or Common-Drain Amplifier
3.4 Common-Gate Amplifier
3.5 Source-Degenerated Current Mirrors
3.6 Cascode Current Mirrors
3.7 Cascode Gain Stage
3.8 MOS Differential Pair and Gain Stage
3.9 Key Points
3.10 References
3.11 Problems

CHAPTER FREQUENCY RESPONSE OF ELECTRONIC CIRCUITS
4.1 Frequency Response of Linear Systems
4.1.1 Magnitude and Phase Response
4.1.2 First-Order Circuits
4.1.3 Second-Order Low-Pass Transfer Functions with Real Poles
4.1.4 Bode Plots
4.1.5 Second-Order Low-Pass Transfer Functions with Complex Poles
4.2 Frequency Response of Elementary Transistor Circuits
4.2.1 High-Frequency MOS Small-Signal Model
4.2.2 Common-Source Amplifier
4.2.3 Miller Theorem and Miller Effect
4.2.4 Zero-Value Time-Constant Analysis
4.2.5 Common-Source Design Examples
4.2.6 Common-Gate Amplifier
4.3 Cascode Gain Stage
4.4 Source-Follower Amplifier
4.5 Differential Pair
4.5.1 High-Frequency T-Model
4.5.2 Symmetric Differential Amplifier
4.5.3 Single-Ended Differential Amplifier
4.5.4 Differential Pair with Active Load
4.6 Key Points
4.7 References
4.8 Problems

CHAPTER FEEDBACK AMPLIFIERS
5.1 Ideal Model of Negative Feedback
5.1.1 Basic Definitions
5.1.2 Gain Sensitivity
5.1.3 Bandwidth
5.1.4 Linearity
5.1.5 Summary
5.2 Dynamic Response of Feedback Amplifiers
5.2.1 Stability Criteria
5.2.2 Phase Margin
5.3 First- and Second-Order Feedback Systems
5.3.1 First-Order Feedback Systems
5.3.2 Second-Order Feedback Systems
5.3.3 Higher-Order Feedback Systems
5.4 Common Feedback Amplifiers
5.4.1 Obtaining the Loop Gain, L(s)
5.4.2 Non-Inverting Amplifier
5.4.3 Transimpedance (Inverting) Amplifiers
5.5 Summary of Key Points
5.6 References
5.7 Problems

CHAPTER BASIC OPAMP DESIGN AND COMPENSATION
6.1 Two-Stage CMOS Opamp
6.1.1 Opamp Gain
6.1.2 Frequency Response
6.1.3 Slew Rate
6.1.4 n-Channel or p-Channel Input Stage
6.1.5 Systematic Offset Voltage
6.2 Opamp Compensation
6.2.1 Dominant-Pole Compensation and Lead Compensation
6.2.2 Compensating the Two-Stage Opamp
6.2.3 Making Compensation Independent of Process and Temperature
6.3 Advanced Current Mirrors
6.3.1 Wide-Swing Current Mirrors
6.3.2 Enhanced Output-Impedance Current Mirrors and Gain Boosting
6.3.3 Wide-Swing Current Mirror with Enhanced Output Impedance
6.3.4 Current-Mirror Symbol
6.4 Folded-Cascode Opamp
6.4.1 Small-Signal Analysis
6.4.2 Slew Rate
6.5 Current Mirror Opamp
6.6 Linear Settling Time Revisited
6.7 Fully Differential Opamps
6.7.1 Fully Differential Folded-Cascode Opamp
6.7.2 Alternative Fully Differential Opamps
6.7.3 Low Supply Voltage Opamps
6.8 Common-Mode Feedback Circuits
6.9 Summary of Key Points
6.10 References
6.11 Problems

CHAPTER BIASING, REFERENCES, AND REGULATORS
7.1 Analog Integrated Circuit Biasing
7.1.1 Bias Circuits
7.1.2 Reference Circuits
7.1.3 Regulator Circuits
7.2 Establishing Constant Transconductance
7.2.1 Basic Constant-Transconductance Circuit
7.2.2 Improved Constant-Transconductance Circuits
7.3 Establishing Constant Voltages and Currents
7.3.1 Bandgap Voltage Reference Basics
7.3.2 Circuits for Bandgap References
7.3.3 Low-Voltage Bandgap Reference
7.3.4 Current Reference
7.4 Voltage Regulation
7.4.1 Regulator Specifications
7.4.2 Feedback Analysis
7.4.3 Low Dropout Regulators
7.5 Summary of Key Points
7.6 References
7.7 Problems

CHAPTER BIPOLAR DEVICES AND CIRCUITS
8.1 Bipolar-Junction Transistors
8.1.1 Basic Operation
8.1.2 Analog Figures of Merit
8.2 Bipolar Device Model Summary
8.3 SPICE Modeling
8.4 Bipolar and BICMOS Processing
8.4.1 Bipolar Processing
8.4.2 Modern SiGe BiCMOS HBT Processing
8.4.3 Mismatch in Bipolar Devices
8.5 Bipolar Current Mirrors and Gain Stages
8.5.1 Current Mirrors
8.5.2 Emitter Follower
8.5.3 Bipolar Differential Pair
8.6 Appendix
8.6.1 Bipolar Transistor Exponential Relationship
8.6.2 Base Charge Storage of an Active BJT
8.7 Summary of Key Points
8.8 References
8.9 Problems

CHAPTER NOISE AND LINEARITY ANALYSIS AND MODELLING
9.1 Time-Domain Analysis
9.1.1 Root Mean Square (rms) Value
9.1.2 SNR
9.1.3 Units of dBm
9.1.4 Noise Summation
9.2 Frequency-Domain Analysis
9.2.1 Noise Spectral Density
9.2.2 White Noise
9.2.3 /f, or Flicker, Noise
9.2.4 Filtered Noise
9.2.5 Noise Bandwidth
9.2.6 Piecewise Integration of Noise
9.2.7 /f Noise Tangent Principle
9.3 Noise Models for Circuit Elements
9.3.1 Resistors
9.3.2 Diodes
9.3.3 Bipolar Transistors
9.3.4 MOSFETS
9.3.5 Opamps
9.3.6 Capacitors and Inductors
9.3.7 Sampled Signal Noise
9.3.8 Input-Referred Noise
9.4 Noise Analysis Examples
9.4.1 Opamp Example
9.4.2 Bipolar Common-Emitter Example
9.4.3 CMOS Differential Pair Example
9.4.4 Fiber-Optic Transimpedance Amplifier Example
9.5 Dynamic Range Performance
9.5.1 Total Harmonic Distortion (THD)
9.5.2 Third-Order Intercept Point (IP3)
9.5.3 Spurious-Free Dynamic Range (SFDR)
9.5.4 Signal-to-Noise and Distortion Ratio (SNDR)
9.6 Key Points
9.7 References
9.8 Problems

CHAPTER COMPARATORS
10.1 Comparator Specifications
10.1.1 Input Offset and Noise
10.1.2 Hysteresis
10.2 Using an Opamp for a Comparator
10.2.1 Input-Offset Voltage Errors
10.3 Charge-Injection Errors
10.3.1 Making Charge-Injection Signal Independent
10.3.2 Minimizing Errors Due to Charge-Injection
10.3.3 Speed of Multi-Stage Comparators
10.4 Latched Comparators
10.4.1 Latch-Mode Time Constant
10.4.2 Latch Offset
10.5 Examples of CMOS and BiCMOS Comparators
10.5.1 Input-Transistor Charge Trapping
10.6 Examples of Bipolar Comparators
10.7 Key Points
10.8 References
10.9 Problems

CHAPTER SAMPLE-AND-HOLD AND TRANSLINEAR CIRCUITS
11.1 Performance of Sample-and-Hold Circuits
11.1.1 Testing Sample and Holds
11.2 MOS Sample-and-Hold Basics
11.3 Examples of CMOS S/H Circuits
11.4 Bipolar and BiCMOS Sample-and-Holds
11.5 Translinear Gain Cell
11.6 Translinear Multiplier
11.7 Key Points
11.8 References
11.9 Problems

CHAPTER CONTINUOUS-TIME FILTERS
12.1 Introduction to Continuous-Time Filters
12.1.1 First-Order Filters
12.1.2 Second-Order Filters
12.2 Introduction to Gm-C Filters
12.2.1 Integrators and Summers
12.2.2 Fully Differential Integrators
12.2.3 First-Order Filter
12.2.4 Biquad Filter
12.3 Transconductors Using Fixed Resistors
12.4 CMOS Transconductors Using Triode Transistors
12.4.1 Transconductors Using a Fixed-Bias Triode Transistor
12.4.2 Transconductors Using Varying Bias-Triode Transistors
12.4.3 Transconductors Using Constant Drain-Source Voltages
12.5 CMOS Transconductors Using Active Transistors
12.5.1 CMOS Pair
12.5.2 Constant Sum of Gate-Source Voltages
12.5.3 Source-Connected Differential Pair
12.5.4 Inverter-Based
12.5.5 Differential-Pair with Floating Voltage Sources
12.5.6 Bias-Offset Cross-Coupled Differential Pairs
12.6 Bipolar Transconductors
12.6.1 Gain-Cell Transconductors
12.6.2 Transconductors Using Multiple Differential Pairs
12.7 BiCMOS Transconductors
12.7.1 Tunable MOS in Triode
12.7.2 Fixed-Resistor Transconductor with a Translinear Multiplier
12.7.3 Fixed Active MOS Transconductor with a Translinear Multiplier
12.8 Active RC and MOSFET-C Filters
12.8.1 Active RC Filters
12.8.2 MOSFET-C Two-Transistor Integrators
12.8.3 Four-Transistor Integrators
12.8.4 R-MOSFET-C Filters
12.9 Tuning Circuitry
12.9.1 Tuning Overview
12.9.2 Constant Transconductance
12.9.3 Frequency Tuning
12.9.4 Q-Factor Tuning
12.9.5 Tuning Methods Based on Adaptive Filtering
12.10 Introduction to Complex Filters
12.10.1 Complex Signal Processing
12.10.2 Complex Operations
12.10.3 Complex Filters
12.10.4 Frequency-Translated Analog Filters
12.11 Key Points
12.12 References
12.13 Problems

CHAPTER DISCRETE-TIME SIGNALS
13.1 Overview of Some Signal Spectra
13.2 Laplace Transforms of Discrete-Time Signals
13.2.1 Spectra of Discrete-Time Signals
13.3 z-Transform
13.4 Downsampling and Upsampling
13.5 Discrete-Time Filters
13.5.1 Frequency Response of Discrete-Time Filters
13.5.2 Stability of Discrete-Time Filters
13.5.3 IIR and FIR Filters
13.5.4 Bilinear Transform
13.6 Sample-and-Hold Response
13.7 Key Points
13.8 References
13.9 Problems

CHAPTER SWITCHED-CAPACITOR CIRCUITS
14.1 Basic Building Blocks
14.1.1 Opamps
14.1.2 Capacitors
14.1.3 Switches
14.1.4 Nonoverlapping Clocks
14.2 Basic Operation and Analysis
14.2.1 Resistor Equivalence of a Switched Capacitor
14.2.2 Parasitic-Sensitive Integrator
14.2.3 Parasitic-Insensitive Integrators
14.2.4 Signal-Flow-Graph Analysis
14.3 Noise in Switched-Capacitor Circuits
14.4 First-Order Filters
14.4.1 Switch Sharing
14.4.2 Fully Differential Filters
14.5 Biquad Filters
14.5.1 Low-Q Biquad Filter
14.5.2 High-Q Biquad Filter
14.6 Charge Injection
14.7 Switched-Capacitor Gain Circuits
14.7.1 Parallel Resistor-Capacitor Circuit
14.7.2 Resettable Gain Circuit
14.7.3 Capacitive-Reset Gain Circuit
14.8 Correlated Double-Sampling Techniques
14.9 Other Switched-Capacitor Circuits
14.9.1 Amplitude Modulator
14.9.2 Full-Wave Rectifier
14.9.3 Peak Detectors
14.9.4 Voltage-Controlled Oscillator
14.9.5 Sinusoidal Oscillator
14.10 Key Points
14.11 References
14.12 Problems

CHAPTER DATA CONVERTER FUNDAMENTALS
15.1 Ideal D/A Converter
15.2 Ideal A/D Converter
15.3 Quantization Noise
15.3.1 Deterministic Approach
15.3.2 Stochastic Approach
15.4 Signed Codes
15.5 Performance Limitations
15.5.1 Resolution
15.5.2 Offset and Gain Error
15.5.3 Accuracy and Linearity
15.6 Key Points
15.7 References
15.8 Problems

CHAPTER NYQUIST-RATE D/A CONVERTERS
16.1 Decoder-Based Converters
16.1.1 Resistor String Converters
16.1.2 Folded Resistor-String Converters
16.1.3 Multiple Resistor-String Converters
16.1.4 Signed Outputs
16.2 Binary-Scaled Converters
16.2.1 Binary-Weighted Resistor Converters
16.2.2 Reduced-Resistance-Ratio Ladders
16.2.3 R-2R-Based Converters
16.2.4 Charge-Redistribution Switched-Capacitor Converters
16.2.5 Current-Mode Converters
16.2.6 Glitches
16.3 Thermometer-Code Converters
16.3.1 Thermometer-Code Current-Mode D/A Converters
16.3.2 Single-Supply Positive-Output Converters
16.3.3 Dynamically Matched Current Sources
16.4 Hybrid Converters
16.4.1 Resistor-Capacitor Hybrid Converters
16.4.2 Segmented Converters
16.5 Key Points
16.6 References
16.7 Problems

CHAPTER NYQUIST-RATE A/D CONVERTERS
17.1 Integrating Converters
17.2 Successive-Approximation Converters
17.2.1 DAC-Based Successive Approximation
17.2.2 Charge-Redistribution A/D
17.2.3 Resistor-Capacitor Hybrid
17.2.4 Speed Estimate for Charge-Redistribution Converters
17.2.5 Error Correction in Successive-Approximation Converters
17.2.6 Multi-Bit Successive-Approximation
17.3 Algorithmic (or Cyclic) A/D Converter
17.3.1 Ratio-Independent Algorithmic Converter
17.4 Pipelined A/D Converters
17.4.1 One-Bit-Per-Stage Pipelined Converter
17.4.2 .5 Bit Per Stage Pipelined Converter
17.4.3 Pipelined Converter Circuits
17.4.4 Generalized k-Bit-Per-Stage Pipelined Converters
17.5 Flash Converters
17.5.1 Issues in Designing Flash A/D Converters
17.6 Two-Step A/D Converters
17.6.1 Two-Step Converter with Digital Error Correction
17.7 Interpolating A/D Converters
17.8 Folding A/D Converters
17.9 Time-Interleaved A/D Converters
17.10 Key Points
17.11 References
17.12 Problems

CHAPTER OVERSAMPLING CONVERTERS
18.1 Oversampling without Noise Shaping
18.1.1 Quantization Noise Modelling
18.1.2 White Noise Assumption
18.1.3 Oversampling Advantage
18.1.4 The Advantage of -Bit D/A Converters
18.2 Oversampling with Noise Shaping
18.2.1 Noise-Shaped Delta-Sigma Modulator
18.2.2 First-Order Noise Shaping
18.2.3 Switched-Capacitor Realization of a First-Order A/D Converter
18.2.4 Second-Order Noise Shaping
18.2.5 Noise Transfer-Function Curves
18.2.6 Quantization Noise Power of -Bit Modulators
18.2.7 Error-Feedback Structure
18.3 System Architectures
18.3.1 System Architecture of Delta-Sigma A/D Converters
18.3.2 System Architecture of Delta-Sigma D/A Converters
18.4 Digital Decimation Filters
18.4.1 Multi-Stage
18.4.2 Single Stage
18.5 Higher-Order Modulators
18.5.1 Interpolative Architecture
18.5.2 Multi-Stage Noise Shaping (MASH) Architecture
18.6 Bandpass Oversampling Converters
18.7 Practical Considerations
18.7.1 Stability
18.7.2 Linearity of Two-Level Converters
18.7.3 Idle Tones
18.7.4 Dithering
18.7.5 Opamp Gain
18.8 Multi-Bit Oversampling Converters
18.8.1 Dynamic Element Matching
18.8.2 Dynamically Matched Current Source D/S Converters
18.8.3 Digital Calibration A/D Converter
18.8.4 A/D with Both Multi-Bit and Single-Bit Feedback
18.9 Third-Order A/D Design Example
18.10 Key Points
18.11 References
18.12 Problems

CHAPTER PHASE-LOCKED LOOPS
19.1 Basic Phase-Locked Loop Architecture
19.1.1 Voltage Controlled Oscillator
19.1.2 Divider
19.1.3 Phase Detector
19.1.4 Loop Filer
19.1.5 The PLL in Lock
19.2 Linearized Small-Signal Analysis
19.2.1 Second-Order PLL Model
19.2.2 Limitations of the Second-Order Small-Signal Model
19.2.3 PLL Design Example
19.3 Jitter and Phase Noise
19.3.1 Period Jitter
19.3.2 P-Cycle Jitter
19.3.3 Adjacent Period Jitter
19.3.4 Other Spectral Representations of Jitter
19.3.5 Probability Density Function of Jitter
19.4 Electronic Oscillators
19.4.1 Ring Oscillators
19.4.2 LC Oscillators
19.4.3 Phase Noise of Oscillators
19.5 Jitter and Phase Noise in PLLS
19.5.1 Input Phase Noise and Divider Phase Noise
19.5.2 VCO Phase Noise
19.5.3 Loop Filter Noise
19.6 Key Points
19.7 References
19.8 Problems
INDEX